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CS2200-CP
Fractional-N Frequency Synthesizer
Features
Delta-Sigma Fractional-N Frequency Synthesis
General Description
The CS2200-CP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2200-CP is based on an analog PLL architecture comprised of a Delta-Sigma Fractional-N Frequency Synthesizer. This architecture allows for frequency synthesis and clock generation from a stable reference clock. The CS2200-CP supports both IC and SPI for full software control. The CS2200-CP is available in a 10-pin MSOP package in Commercial (-10 C to +70 C) grade. Customer development kits are also available for device evaluation. Please see "Ordering Information" on page 25 for complete details.

Generates a Low Jitter 6 - 75 MHz Clock from an 8 - 75 MHz Reference Clock Highly Accurate PLL Multiplication Factor - Maximum Error Less Than 1 PPM ICTM / SPITM Control Port Configurable Auxiliary Output - Buffered Reference Clock - PLL Lock Indication - Duplicate PLL Output Flexible Sourcing of Reference Clock - External Oscillator or Clock Source - Supports Inexpensive Local Crystal Minimal Board Space Required - No External Analog Loop-filter Components
-
3.3 V
Timing Reference
IC/SPI Software Control
IC / SPI
PLL Output PLL Lock Indicator
Auxiliary Output
8 MHz to 75 MHz Low-Jitter Timing Reference
Phase Comparator
Internal Loop Filter
Voltage Controlled Oscillator
6 to 75 MHz PLL Output
Fractional-N Divider
Delta-Sigma Modulator
N
Output to Input Clock Ratio
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
AUG '09 DS759F1
CS2200-CP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4 2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6 AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7 CONTROL PORT SWITCHING CHARACTERISTICS- IC FORMAT ................................................... 8 CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ................................................. 9 4. ARCHITECTURE OVERVIEW ............................................................................................................. 10 4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 10 5. APPLICATIONS ................................................................................................................................... 11 5.1 Timing Reference Clock Input ........................................................................................................ 11 5.1.1 Internal Timing Reference Clock Divider ............................................................................... 11 5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 12 5.1.3 External Reference Clock (REF_CLK) .................................................................................. 12 5.2 Output to Input Frequency Ratio Configuration ............................................................................. 12 5.2.1 User Defined Ratio (RUD) ..................................................................................................... 12 5.2.2 Ratio Modifier (R-Mod) .......................................................................................................... 13 5.2.3 Effective Ratio (REFF) .......................................................................................................... 13 5.2.4 Ratio Configuration Summary ............................................................................................... 14 5.3 PLL Clock Output ........................................................................................................................... 14 5.4 Auxiliary Output .............................................................................................................................. 15 5.5 Clock Output Stability Considerations ............................................................................................ 15 5.5.1 Output Switching ................................................................................................................... 15 5.5.2 PLL Unlock Conditions .......................................................................................................... 15 5.6 Required Power Up Sequencing .................................................................................................... 16 6. SPI / IC CONTROL PORT ................................................................................................................... 16 6.1 SPI Control ..................................................................................................................................... 16 6.2 IC Control ...................................................................................................................................... 16 6.3 Memory Address Pointer ............................................................................................................... 18 6.3.1 Map Auto Increment .............................................................................................................. 18 7. REGISTER QUICK REFERENCE ........................................................................................................ 18 8. REGISTER DESCRIPTIONS ................................................................................................................ 19 8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 19 8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 19 8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 19 8.2 Device Control (Address 02h) ........................................................................................................ 19 8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 19 8.2.2 Auxiliary Output Disable (AuxOutDis) ................................................................................... 19 8.2.3 PLL Clock Output Disable (ClkOutDis) .................................................................................. 20 8.3 Device Configuration 1 (Address 03h) ........................................................................................... 20 8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 20 8.3.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 20 8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1) ........................................................ 21 8.4 Global Configuration (Address 05h) ............................................................................................... 21 8.4.1 Device Configuration Freeze (Freeze) ................................................................................ 21 8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 21 8.5 Ratio (Address 06h - 09h) .............................................................................................................. 21 8.6 Function Configuration 1 (Address 16h) ........................................................................................ 22 8.6.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 22 8.6.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 22 2 DS759F1
CS2200-CP
8.7 Function Configuration 2 (Address 17h) ........................................................................................ 22 8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22 9. CALCULATING THE USER DEFINED RATIO .................................................................................... 23 9.1 12.20 Format .................................................................................................................................. 23 10. PACKAGE DIMENSIONS .................................................................................................................. 24 THERMAL CHARACTERISTICS ......................................................................................................... 24 11. ORDERING INFORMATION .............................................................................................................. 25 12. REFERENCES .................................................................................................................................... 25 13. REVISION HISTORY .......................................................................................................................... 26
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 5 Figure 2. Control Port Timing - IC Format .................................................................................................. 8 Figure 3. Control Port Timing - SPI Format (Write Only) ............................................................................ 9 Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 10 Figure 5. Internal Timing Reference Clock Divider ................................................................................... 11 Figure 6. REF_CLK Frequency vs a Fixed CLK_OUT .............................................................................. 11 Figure 7. External Component Requirements for Crystal Circuit .............................................................. 12 Figure 8. Ratio Feature Summary ............................................................................................................. 14 Figure 9. PLL Clock Output Options ......................................................................................................... 14 Figure 10. Auxiliary Output Selection ........................................................................................................ 15 Figure 11. Control Port Timing in SPI Mode ............................................................................................. 17 Figure 12. Control Port Timing, IC Write .................................................................................................. 17 Figure 13. Control Port Timing, IC Aborted Write + Read ....................................................................... 17
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 13 Table 2. Example 12.20 R-Values ............................................................................................................ 23
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CS2200-CP 1. PIN DESCRIPTION
VD GND CLK_OUT AUX_OUT TST_IN
1 2 3 4 5
10 9 8 7 6
SDA/CDIN SCL/CCLK AD0/CS XTI/REF_CLK XTO
Pin Name
VD GND CLK_OUT AUX_OUT TST_IN XTO XTI/REF_CLK AD0/CS SCL/CCLK SDA/CDIN
#
1 2 3 4 5 6 7 8 9
Pin Description
Digital Power (Input) - Positive power supply for the digital and analog sections. Ground (Input) - Ground reference. PLL Clock Output (Output) - PLL clock output. Auxiliary Output (Output) - This pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on register configuration. Test Input (Input) - This pin is for factory test purposes and must be connected to GND for proper operation. Crystal Connections (XTI/XTO) / Timing Reference Clock Input (REF_CLK) (Input/Output) XTI/XTO are I/O pins for an external crystal which may be used to generate the low-jitter PLL input clock. REF_CLK is an input for an externally generated low-jitter reference clock. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode. CS is the chip select signal in SPI Mode. Control Port Clock (Input) - SCL/CCLK is the serial clock for the serial control port in IC and SPI mode.
10 Serial Control Data (Input/Output) - SDA is the data I/O line in IC Mode. CDIN is the input data line for the control port interface in SPI Mode.
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CS2200-CP 2. TYPICAL CONNECTION DIAGRAM
Note1 Notes: 1. Resistors required for I2C operation. 0.1 F
2 k 2 k
1 F
+3.3 V
VD SCL/CCLK System MicroController SDA/CDIN AD0/CS CLK_OUT To circuitry which requires a low-jitter clock
CS2200-CP
AUX_OUT
1 or 2
To other circuitry or Microcontroller
XTI/REF_CLK XTO
GND
TST_IN
Low-Jitter Timing Reference
REF_CLK
1
N.C. x
XTO
or Crystal XTI
2
XTO
40 pF 40 pF
Figure 1. Typical Connection Diagram
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CS2200-CP 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
GND = 0 V; all voltages with respect to ground. (Note 1) Parameters
DC Power Supply Ambient Operating Temperature (Power Applied) Commercial Grade TAC -10 +70 C
Symbol
VD
Min
3.1
Typ
3.3
Max
3.5
Units
V
Notes: 1. Device functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability.
ABSOLUTE MAXIMUM RATINGS
GND = 0 V; all voltages with respect to ground. Parameters
DC Power Supply Input Current Digital Input Voltage (Note 2) Ambient Operating Temperature (Power Applied) Storage Temperature
Symbol
VD IIN VIN TA Tstg
Min
-0.3 -0.3 -55 -65
Max
6.0 10 VD + 0.4 125 150
Units
V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 2. The maximum over/under voltage is limited by the input current except on the power supply pin.
DC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10C to +70C (Commercial Grade). Parameters
Power Supply Current - Unloaded Power Dissipation - Unloaded Input Leakage Current Input Capacitance High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOH = -1.2 mA) Low-Level Output Voltage (IOH = 1.2 mA) (Note 3) (Note 3)
Symbol
ID PD IIN IC VIH VIL VOH VOL
Min
70% 80% -
Typ
12 40 8 -
Max
18 60 10 30% 20%
Units
mA mW A pF VD VD VD VD
Notes: 3. To calculate the additional current consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. For example, fCLK_OUT (49.152 MHz) * CL (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to these loading conditions on CLK_OUT.
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CS2200-CP AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10C to +70C (Commercial Grade); CL = 15 pF. Parameters
Crystal Frequency Fundamental Mode XTAL Reference Clock Input Frequency
Symbol
fXTAL
Conditions RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00 RefClkDiv[1:0] = 10 RefClkDiv[1:0] = 01 RefClkDiv[1:0] = 00
Min
8 16 32 8 16 32 45 8 6
Typ
50 1.7 1.7 70 50 175 1 -
Max
14 28 50 14 28 56 55 14 75 55 3.0 3.0 3 0.5
Units
MHz MHz MHz MHz MHz MHz % MHz MHz % ns ns ps rms ps rms ps rms ms ppm
fREF_CLK
Reference Clock Input Duty Cycle Internal System Clock Frequency PLL Clock Output Frequency PLL Clock Output Duty Cycle Clock Output Rise Time Clock Output Fall Time Period Jitter Base Band Jitter (100 Hz to 40 kHz) Wide Band JItter (100 Hz Corner) PLL Lock Time - REF_CLK Output Frequency Synthesis Resolution (Note 7)
DREF_CLK fSYS_CLK fCLK_OUT tOD tOR tOF tJIT Measured at VD/2 20% to 80% of VD 80% to 20% of VD (Note 4) (Notes 4, 5) (Notes 4, 6) tLR ferr fREF_CLK = 8 to 75 MHz
45 0
Notes: 4. fCLK_OUT = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11. 5. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd order 100 Hz to 40 kHz bandpass filter. 6. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd order 100 Hz Highpass filter. 7. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the reference clock.
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CS2200-CP CONTROL PORT SWITCHING CHARACTERISTICS- IC FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF. Parameter
SCL Clock Frequency Bus Free-Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup Time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling Delay from Supply Voltage Stable to Control Port Ready (Note 8)
Symbol
fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp tack tdpor
Min
4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 100
Max
100 1 300 1000 -
Unit
kHz s s s s s s ns s ns s ns s
Notes: 8. Data must be held for sufficient time to bridge the transition time, tf, of SCL.
VD
t dpor
Repeated Start
Stop
SDA t buf t hdst t high t hdst tf t susp
SCL
Stop
Start t low t hdd t sud t sust tr
Figure 2. Control Port Timing - IC Format
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CS2200-CP CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; CL = 20 pF. Parameter
CCLK Clock Frequency CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Delay from Supply Voltage Stable to Control Port Ready (Note 10) (Note 11) (Note 11) (Note 9)
Symbol
fccllk tspi tcsh tcss tscl tsch tdsu tdh tr2 tf2 tdpor
Min
500 1.0 20 66 66 40 15 100
Max
6 100 100 -
Unit
MHz ns s ns ns ns ns ns ns ns s
Notes: 9. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times. 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For fcclk < 1 MHz.
VD
tdpor
CS t spi CCLK t r2
CDIN
t css
t scl
t sch
t csh
t f2
t dsu
tdh
Figure 3. Control Port Timing - SPI Format (Write Only)
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CS2200-CP 4. ARCHITECTURE OVERVIEW
4.1 Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2200 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolution for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input clock ratio is the value of N that is applied to the delta-sigma modulator (see Figure 4). The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fractional-N divided clock with the original timing reference and generates a control signal. The control signal is filtered by the internal loop filter to generate the VCO's control voltage which sets its output frequency. The delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the VCO output (thus the one's density of the modulator sets the fractional value). This allows the design to be optimized for very fast lock times for a wide range of output frequencies without the need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference clock should be stable and jitter-free.
Timing Reference Clock
Phase Comparator
Internal Loop Filter
Voltage Controlled Oscillator
PLL Output
Fractional-N Divider
Delta-Sigma Modulator
N
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer
10
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CS2200-CP 5. APPLICATIONS
5.1 Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL output the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock directly affects the performance of the PLL and hence the quality of the PLL output.
5.1.1
Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on the XTI/REF_CLK pin. The CS2200 supports the wider external frequency range by offering an internal divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls within the valid range as indicated in "AC Electrical Characteristics" on page 7.
Timing Reference Clock Divider
Internal Timing Reference Clock 8 MHz < SysClk < 14 MHz
Timing Reference Clock XTI/REF_CLK 8 MHz < RefClk <
50 MHz (XTI) 58 MHz (REF_CLK)
/1 /2 /4
Fractional-N Frequency Synthesizer
PLL Output
RefClkDiv[1:0]
N
Figure 5. Internal Timing Reference Clock Divider It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent upon its configuration as either a crystal connection or external clock input. See the "AC Electrical Characteristics" on page 7 for more details. For the lowest possible output jitter, attention should be paid to the absolute frequency of the Timing Reference Clock relative to the PLL Output frequency (CLK_OUT). To minimize output jitter, the Timing Reference Clock frequency should be chosen such that fRefClk is at least +/-15 kHz from fCLK_OUT*N/32 where N is an integer. Figure 6 shows the effect of varying the RefClk frequency around fCLK_OUT*N/32. It should be noted that there will be a jitter null at the zero point when N = 32 (not shown in Figure 6). An example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
f L f RefClk f H where:
180 f CLK__OUT *32/N CLK__OUT Jitter
Typical Base Band Jitter (psec)
f L = f CLK_OUT x 31 + 15kHz ----32 = 12.288MHz x 0.96875 + 15kHz = 11.919MHz
160
140
120
100 -15 kHz +15 kHz
and
f H = f CLK_OUT x 32 - 15kHz ----32 = 12.288MHz x 1 + 15kHz = 12.273MHz
80
60
40
20 -80 -60 -40 -20 0 20 40 60 80
Normalized REF__CLK Frequency (kHz)
Figure 6. REF_CLK Frequency vs a Fixed CLK_OUT
Referenced Control Register Location
RefClkDiv[1:0] ......................."Reference Clock Input Divider (RefClkDiv[1:0])" on page 22
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5.1.2 Crystal Connections (XTI and XTO)
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 7. As shown, nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer to the "AC Electrical Characteristics" on page 7 for the allowed crystal frequency range.
XTI
XTO
40 pF
40 pF
Figure 7. External Component Requirements for Crystal Circuit
5.1.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the reference clock source and XTO should be left unconnected or pulled low through a 47 k resistor to GND.
5.2 5.2.1
Output to Input Frequency Ratio Configuration User Defined Ratio (RUD)
The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number, stored in the Ratio register set, which determines the basis for the desired input to output clock ratio. The 32-bit RUD is represented in a 12.20 format where the 12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See "Calculating the User Defined Ratio" on page 23 for more information. The status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. Therefore RUD is simply the desired ratio of the output to input clock frequencies.
Referenced Control Register Location Ratio......................................"Ratio (Address 06h - 09h)" on page 21
12
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5.2.2 Ratio Modifier (R-Mod)
The Ratio Modifier is used to internally multiply/divide the RUD (the Ratio stored in the register space remains unchanged). The available options for RMOD are summarized in Table 1 on page 13. The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio (REFF), see "Effective Ratio (REFF)" on page 13. If R-Mod is not desired, RModSel[2:0] should be left at its default value of `000', which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio modifier. RModSel[2:0]
000 001 010 011 100 101 110 111
Ratio Modifier 1 2 4 8 0.5 0.25 0.125 0.0625 Table 1. Ratio Modifier
Referenced Control
Register Location
Ratio......................................"Ratio (Address 06h - 09h)" on page 21 RModSel[2:0] ........................"R-Mod Selection (RModSel[2:0])" section on page 20
5.2.3
Effective Ratio (REFF)
The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as previously described. REFF is calculated as follows: REFF = RUD * RMOD To simplify operation the device handles some of the ratio calculation functions automatically (such as when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need to be altered to account for internal dividers. Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For example if RUD is 1024 an RMOD of 8 would produce an REFF value of 8192 which exceeds the 4096 limit of the 12.20 format. In all cases, the maximum and minimum allowable values for REFF are dictated by the frequency limits for both the input and output clocks as shown in the "AC Electrical Characteristics" on page 7.
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5.2.4 Ratio Configuration Summary
The RUD is the user defined ratio stored in the register space. R-Mod is applied if selected. The user defined ratio, and ratio modifier make up the effective ratio REFF, the final calculation used to determine the output to input clock ratio. The effective ratio is then corrected for the internal dividers. The conceptual diagram in Figure 8 summarizes the features involved in the calculation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesizer.
Timing Reference Clock (XTI/REF_CLK)
Divide Effective Ratio REFF
RefClkDiv[1:0]
SysClk User Defined Ratio RUD Ratio Ratio Format 12.20 RModSel[2:0] Ratio Modifier RefClkDiv[1:0] N
Frequency Synthesizer
PLL Outpu
R Correction
Figure 8. Ratio Feature Summary
Referenced Control Register Location Ratio......................................"Ratio (Address 06h - 09h)" on page 21 RModSel[2:0] ........................"R-Mod Selection (RModSel[2:0])" section on page 20 RefClkDiv[1:0] ......................."Reference Clock Input Divider (RefClkDiv[1:0])" on page 22
5.3
PLL Clock Output
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer. The driver can be set to high-impedance with the ClkOutDis bit. The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state CLK_OUT may then be unreliable during an unlock condition.
ClkOutUnl PLL Locked/Unlocked
0
0
2:1 Mux
1
0 PLL Clock Output PLLClkOut
ClkOutDis
2:1 Mux
PLL Output 1
PLL Clock Output Pin (CLK_OUT)
Figure 9. PLL Clock Output Options
Referenced Control Register Location ClkOutUnl.............................."Enable PLL Clock Output on Unlock (ClkOutUnl)" on page 22 ClkOutDis .............................."PLL Clock Output Disable (ClkOutDis)" on page 20
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5.4 Auxiliary Output
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 10, to one of three signals: reference clock (RefClk), additional PLL clock output (CLK_OUT), or a PLL lock indicator (Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is then used to control the output driver type and polarity of the LOCK signal (see section 8.6.1 on page 22). If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit.
AuxOutSrc[1:0]
Timing Reference Clock (RefClk)
AuxOutDis
PLL Clock Output (PLLClkOut)
3:1 Mux
Auxiliary Output Pin (AUX_OUT)
PLL Lock/Unlock Indication (Lock)
AuxLockCfg
Figure 10. Auxiliary Output Selection
Referenced Control Register Location AuxOutSrc[1:0]......................"Auxiliary Output Source Selection (AuxOutSrc[1:0])" on page 20 AuxOutDis ............................."Auxiliary Output Disable (AuxOutDis)" on page 19 AuxLockCfg..........................."AUX PLL Lock Output Configuration (AuxLockCfg)" section on page 22
5.5 5.5.1
Clock Output Stability Considerations Output Switching
CS2200 is designed such that re-configuration of the clock routing functions do not result in a partial clock period on any of the active outputs (CLK_OUT and/or AUX_OUT). In particular, enabling or disabling an output, changing the auxiliary output source between REF_CLK and CLK_OUT, and the automatic disabling of the output(s) during unlock will not cause a runt or partial clock period. The following exceptions/limitations exist: * * * Enabling/disabling AUX_OUT when AuxOutSrc[1:0] = 11 (unlock indicator). Switching AuxOutSrc[1:0] to or from 11 (unlock indicator) (Transitions between AuxOutSrc[1:0] = [00,10] will not produce a glitch). Changing the ClkOutUnl bit while the PLL is in operation.
When any of these exceptions occur, a partial clock period on the output may result.
5.5.2
PLL Unlock Conditions
Certain changes to the clock inputs and registers can cause the PLL to lose lock which will affect the presence the clock signal on CLK_OUT. The following outlines which conditions cause the PLL to go unlocked: * Changes made to the registers which affect the Fraction-N value that is used by the Frequency Syn15
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thesizer. This includes all the bits shown in Figure 8 on page 14. * Any discontinuities on the Timing Reference Clock, REF_CLK.
5.6
Required Power Up Sequencing
* * Apply power to the device. The output pins will remain low until the device is configured with a valid ratio via the control port. Write the desired operational configurations. The EnDevCfg1 and EnDevCfg2 bits must be set to 1 during the initialization register writes; the order does not matter. - The Freeze bit may be set prior to this step and cleared afterward to ensure all settings take effect at the same time.
6. SPI / IC CONTROL PORT
The control port is used to access the registers and allows the device to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to device inputs and outputs. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates with either the SPI or IC interface, with the CS2200 acting as a slave device. SPI Mode is selected if there is a high-to-low transition on the AD0/CS pin after power-up. IC Mode is selected by connecting the AD0/CS pin through a resistor to VD or GND, thereby permanently selecting the desired AD0 bit address state. In both modes the EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING: All "Reserved" registers must maintain their default state to ensure proper functional operation.
Referenced Control Register Location EnDevCfg1 ............................"Enable Device Configuration Registers 1 (EnDevCfg1)" on page 21 EnDevCfg2 ............................"Enable Device Configuration Registers 2 (EnDevCfg2)" section on page 21
6.1
SPI Control
In SPI Mode, CS is the chip select signal; CCLK is the control port bit clock (sourced from a microcontroller), and CDIN is the input data line from the microcontroller. Data is clocked in on the rising edge of CCLK. The device only supports write operations. Figure 11 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The first eight bits on CDIN form the chip address and must be 10011110. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. There is MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will automatically increment after each byte is read or written, allowing block writes of successive registers.
6.2
IC Control
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. There is no CS pin. The AD0 pin forms the least-significant bit of the chip address and should be connected to VD or GND as appropriate. The state of the AD0 pin should be maintained throughout operation of the device.
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CS2200-CP
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CCLK
CHIP ADDRESS MAP BYTE
1 0
INCR
DATA
1 0 7 6 1 0 7
DATA +n
6 1 0
CDIN
1
0
0
1
1
1
6
5
4
3
2
Figure 11. Control Port Timing in SPI Mode
The signal timings for a read and write cycle are shown in Figure 12 and Figure 13. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS2200 after a Start condition consists of the 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100111 followed by the logic state of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS2200 after each input byte is read and is input from the microcontroller after each transmitted byte.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
0
INCR
DATA
1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
1
0
0
1
1
1
AD0
6
5
4
3
2
ACK START
ACK
ACK
ACK STOP
Figure 12. Control Port Timing, IC Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 1 1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
1 1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 13. Control Port Timing, IC Aborted Write + Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown in Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 100111x0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. DS759F1 17
CS2200-CP
Send stop condition, aborting write. Send start condition. Send 100111x1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
6.3
Memory Address Pointer
The Memory Address Pointer (MAP) byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details.
6.3.1
Map Auto Increment
The device has MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive IC writes or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of successive registers.
7. REGISTER QUICK REFERENCE
This table shows the register and bit names with their associated default values. EnDevCfg1 and EnDevCfg2 bits must be set to 1 for normal operation. WARNING: All "Reserved" registers must maintain their default state to ensure proper functional operation. Adr
p 19 02h Device Ctrl p 19 03h Device Cfg 1 p 20 05h Global Cfg p 21 06h - 32-Bit Ratio 09h 16h Funct Cfg 1 p 22 17h Funct Cfg 2 p 22
Name
7
6
5
4
3
2
1
0
Revision0 x ClkOutDis 0 EnDevCfg1 0 EnDevCfg2 0 MSB-7 MSB-15 LSB+8 LSB Reserved 0 Reserved 0
01h Device ID
Device4 Device3 Device2 Device1 Device0 Revision2 Revision1 0 0 0 0 0 x x Unlock Reserved Reserved Reserved Reserved Reserved AuxOutDis x x x 0 0 0 0 RModSel2 RModSel1 RModSel0 Reserved Reserved AuxOutSrc1 AuxOutSrc0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Freeze Reserved Reserved 0 0 0 0 0 0 0 MSB ........................................................................................................................... MSB-8 ........................................................................................................................... LSB+15 ........................................................................................................................... LSB+7 ........................................................................................................................... Reserved AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved 0 0 0 0 0 0 0 Reserved Reserved Reserved ClkOutUnl Reserved Reserved Reserved 0 0 0 0 0 0 0
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CS2200-CP 8. REGISTER DESCRIPTIONS
In IC Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All "Reserved" registers must maintain their default state to ensure proper functional operation. The default state of each bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the "Register Quick Reference" on page 18. Control port mode is entered when the device recognizes a valid chip address input on its IC/SPI serial control pins and the EnDevCfg1 and EnDevCfg2 bits are set to 1.
8.1
Device I.D. and Revision (Address 01h)
6 Device3 5 Device2 4 Device1 3 Device0 2 Revision2 1 Revision1 0 Revision0
7 Device4
8.1.1
Device Identification (Device[4:0]) - Read Only
I.D. code for the CS2200.
Device[4:0] 00000 Device CS2200.
8.1.2
Device Revision (Revision[2:0]) - Read Only
CS2200 revision level.
REVID[2:0] 100 110 Revision Level B2 and B3 C1
8.2
Device Control (Address 02h)
7 Unlock 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 AuxOutDis 0 ClkOutDis
8.2.1
Unlock Indicator (Unlock) - Read Only
Indicates the lock state of the PLL.
Unlock 0 1 PLL Lock State PLL is Locked. PLL is Unlocked.
8.2.2
Auxiliary Output Disable (AuxOutDis)
This bit controls the output driver for the AUX_OUT pin.
AuxOutDis 0 1 Application: Output Driver State AUX_OUT output driver enabled. AUX_OUT output driver set to high-impedance. "Auxiliary Output" on page 15
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CS2200-CP
8.2.3 PLL Clock Output Disable (ClkOutDis)
This bit controls the output driver for the CLK_OUT pin.
ClkOutDis 0 1 Application: Output Driver State CLK_OUT output driver enabled. CLK_OUT output driver set to high-impedance. "PLL Clock Output" on page 14
8.3
Device Configuration 1 (Address 03h)
6 RModSel1 5 RModSel0 4 Reserved 3 Reserved 2 AuxOutSrc1 1 AuxOutSrc0 0 EnDevCfg1
7 RModSel2
8.3.1
R-Mod Selection (RModSel[2:0])
Selects the R-Mod value, which is used as a factor in determining the PLL's Fractional N.
RModSel[2:0] 000 001 010 011 100 101 110 111 Application: R-Mod Selection Left-shift R-value by 0 (x 1). Left-shift R-value by 1 (x 2). Left-shift R-value by 2 (x 4). Left-shift R-value by 3 (x 8). Right-shift R-value by 1 (/ 2). Right-shift R-value by 2 (/ 4). Right-shift R-value by 3 (/ 8). Right-shift R-value by 4 (/ 16). "Ratio Modifier (R-Mod)" on page 13
8.3.2
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0] 00 01 10 11 Application: Auxiliary Output Source RefClk. Reserved. CLK_OUT. PLL Lock Status Indicator. "Auxiliary Output" on page 15
Note: When set to 11, AuxLckCfg sets the polarity and driver type. See "AUX PLL Lock Output Configuration (AuxLockCfg)" on page 22.
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CS2200-CP
8.3.3 Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur.
EnDevCfg1 0 1 Application: Register State Disabled. Enabled. "SPI / IC Control Port" on page 16
Note: EnDevCfg2 must also be set to enable control port mode. See "SPI / IC Control Port" on page 16.
8.4
Global Configuration (Address 05h)
6 Reserved 5 Reserved 4 Reserved 3 Freeze 2 Reserved 1 Reserved 0 EnDevCfg2
7 Reserved
8.4.1
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h) but keeps them from taking effect until this bit is cleared.
FREEZE 0 1 Device Control and Configuration Registers Register changes take effect immediately. Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without the changes taking effect until after the FREEZE bit is cleared.
8.4.2
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg bits can be set in any order and at any time during the control port access sequence, however they must both be set before normal operation can occur.
EnDevCfg2 0 1 Application: Register State Disabled. Enabled. "SPI / IC Control Port" on page 16
Note: EnDevCfg1 must also be set to enable control port mode. See "SPI / IC Control Port" on page 16.
8.5
Ratio (Address 06h - 09h)
6 5 4 3 2 1 ................................................................................................................................................... ................................................................................................................................................... ................................................................................................................................................... ................................................................................................................................................... 0 MSB-7 MSB-15 LSB+8 LSB
7 MSB MSB-8 LSB+15 LSB+7
These registers contain the User Defined Ratio as shown in the "Register Quick Reference" section on page 18. These 4 registers form a single 32-bit ratio value as shown above. See "Output to Input Frequency Ratio Configuration" on page 12 and "Calculating the User Defined Ratio" on page 23 for more details. DS759F1 21
CS2200-CP
8.6 Function Configuration 1 (Address 16h)
6 AuxLockCfg 5 Reserved 4 RefClkDiv1 3 RefClkDiv0 2 Reserved 1 Reserved 0 Reserved 7 Reserved
8.6.1
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg 0 1 Application: AUX_OUT Driver Configuration Push-Pull, Active High (output `high' for unlocked condition, `low' for locked condition). Open Drain, Active Low (output `low' for unlocked condition, high-Z for locked condition). "Auxiliary Output" on page 15
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. Therefore, the pin polarity is defined relative to the unlock condition.
8.6.2
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0] 00 01 10 11 Application: Reference Clock Input Divider / 4. / 2. / 1. Reserved. "Internal Timing Reference Clock Divider" on page 11 REF_CLK Frequency Range 32 MHz to 56 MHz (50 MHz with XTI) 16 MHz to 28 MHz 8 MHz to 14 MHz
8.7
Function Configuration 2 (Address 17h)
6 Reserved 5 Reserved 4 ClkOutUnl 3 Reserved 2 Reserved 1 Reserved 0 Reserved
7 Reserved
8.7.1
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl 0 1 Application: Clock Output Enable Status Clock outputs are driven `low' when PLL is unlocked. Clock outputs are always enabled (results in unpredictable output when PLL is unlocked). "PLL Clock Output" on page 14
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CS2200-CP 9. CALCULATING THE USER DEFINED RATIO
Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User Defined Ratio. This section is for those who are not interested in the software or who are developing their systems without the aid of the evaluation kit.
Most calculators do not interpret the fixed point binary representation which the CS2200 uses to define the output to input clock ratio (see Section 5.2.1 on page 12); However, with a simple conversion we can use these tools to generate a binary or hex value which can be written to the Ratio register.
9.1
12.20 Format
To calculate the User Defined Ratio (RUD) to store in the register(s), divide the desired output clock frequency by the given input clock (RefClk). Then multiply the desired ratio by the scaling factor of 220 to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and write to the register. A few examples have been provided in Table 2. Desired Output to Input Clock Ratio (output clock/input clock)
12.288 MHz/10 MHz=1.2288 11.2896 MHz/44.1 kHz=256
Scaled Decimal Representation = (output clock/input clock) * 220 1288490 268435456
Hex Representation of Binary RUD 00 13 A9 2A 10 00 00 00
Table 2. Example 12.20 R-Values
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CS2200-CP 10.PACKAGE DIMENSIONS 10L MSOP (3 mm BODY) PACKAGE DRAWING (Note 1)
N
D c E A2 A1
L
E11 A
e b END VIEW SIDE VIEW SEATING PLANE
L1
123
TOP VIEW
DIM
A A1 A2 b c D E E1 e L L1
MIN
-0 0.0295 0.0059 0.0031 ----0.0157 --
INCHES NOM
-----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF
MAX
0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 --
MIN
-0 0.75 0.15 0.08 ----0.40 --
MILLIMETERS NOM
-----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF
NOTE MAX
1.10 0.15 0.95 0.30 0.23 ----0.80 --
4, 5 2 3
Notes: 1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension.
THERMAL CHARACTERISTICS
Parameter
Junction to Ambient Thermal Impedance JEDEC 2-Layer JEDEC 4-Layer
Symbol
JA JA
Min
-
Typ
170 100
Max
-
Units
C/W C/W
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DS759F1
CS2200-CP 11.ORDERING INFORMATION
Product
CS2200-CP CS2200-CP CDK2000
Description
Clocking Device Clocking Device Evaluation Platform
Package
10L-MSOP 10L-MSOP -
Pb-Free Yes Yes Yes
Grade Commercial -
Temp Range Container
-10 to +70C -10 to +70C Rail Tape and Reel -
Order# CS2200CP-CZZ CS2200CP-CZZR CDK2000-CLK
12.REFERENCES
1. Audio Engineering Society AES-12id-2006: "AES Information Document for digital audio measurements Jitter performance specifications," May 2007. 2. Philips Semiconductor, "The IC-Bus Specification: Version 2," Dec. 1998. http://www.semiconductors.philips.com
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25
CS2200-CP 13.REVISION HISTORY
Release
F1
Changes
Updated Period Jitter specification in "AC Electrical Characteristics" on page 7. Updated Crystal and Ref Clock Frequency specifications in "AC Electrical Characteristics" on page 7. Updated "Internal Timing Reference Clock Divider" on page 11 and added Figure 6 on page 11.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. IC is a trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.
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DS759F1

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